Phase-locked-loop (PLL) devices are control systems that generate signals having a fixed relationship to the phase of a reference signal. Typically, a phase-locked loop device generates a desired signal in response to both the frequency and the phase of the reference signal as well as a control signal. Often this includes raising or lowering the frequency of a frequency generator, such as a digitally controlled oscillator (DCO), until a modified form (a fraction, for example) of the oscillator output signal is matched with the reference signal in both frequency and phase. Phase-locked loops are widely used in radio, telecommunications, computers, and other electronic applications.
PLL devices generally include a phase detector (such as a binary phase detector, for example) which detects whether the phase of the modified output signal (e.g., the output of the DCO divided by a divider value) leads or lags the phase of the reference signal. This allows the PLL device to “lock” to the desired frequency, and provide a constant PLL output frequency. The DCO raises or lowers its output frequency based on the output of the phase detector, for example.
However, the properties of binary phase detectors (a.k.a. bang-bang phase detectors) may be highly non-linear. For example, the response of the phase frequency detection may not depend on the actual phase error, but rather on the sign of the error. This presents limits on the response capabilities of the PLL, including inhibiting frequency modulation applications of the PLL. For example, high data-rate frequency shift keying (FSK) modulation uses high-frequency deviation values, beyond the capability of a typical binary phase detector. Additionally, the non-linearity of a binary phase detector implies that the instantaneous gain of the PLL depends on the instantaneous phase error, which makes the overall bandwidth of the PLL not constant, but rather unpredictable.